6.13 System Interface Bus Encoding
SysState[2:0] Encoding
The processor provides a processor coherency state response by driving the targeted secondary cache block tag quality indication on SysState[2], driving the targeted secondary cache block former state on SysState[1:0] and asserting SysStateVal* for one SysClk cycle. Table 6-24 presents the encoding of the SysState[2:0] bus when SysStateVal* is asserted.
Table 6-24 Encoding of SysState[2:0] when SysStateVal* Asserted
When SysStateVal* is negated, SysState[0] indicates if a processor coherency data response is ready for issue. Table 6-25 presents the encoding of the SysState[2:0] bus when SysStateVal* is negated.
Table 6-25 Encoding of SysState[2:0] When SysStateVal* Negated
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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